Course · SFT6330
Circuit design language - Verilog
Course information
- Course code
- SFT6330
- Credits (ECTS)
- 6
- L + S + Lab
- 30 + 30 + 0
- Year / semester
- Year 3 / semester 6
- Level of course
- Bachelor's degree
- Component
- Elective component (EC)
- Cycle
- PD
- Final assessment
- Examination
- Educational programme
- 6B06106 Computing and software
- Curriculum
- Вычислительная техника и программное обеспечение (2024-2028)
Course description
The Circuit design language - Verilog course covers the basic concepts and syntax of the language and its application to the modeling and design of digital circuits. During the course, students study the following topics:
1. Introduction to Verilog: history, basic concepts, module structure.
2. Verilog syntax: description of modules, ports, variables, operators and expressions.
3. Modeling of digital circuits: creation of combinational and sequential logic circuits.
4. Testing and Debugging: Using simulators to verify that circuits are working correctly.
5. Verilog synthesis: converting Verilog code into physical elements on a chip.
6. FPGA Circuit Design: Using Verilog to Program Programmable Logic Devices.
Student workload
| Type of work | Hours per week | Weeks | Total hours per semester |
|---|---|---|---|
| Lectures (L) | 2 | 15 | 30 |
| Seminars and practical classes (S) | 2 | 15 | 30 |
| Independent work under instructor supervision | 1 | 15 | 15 |
| Independent student work | 7 | 15 | 105 |
| Total | 180 |
1 credit = 30 academic hours; a semester lasts 15 weeks.
Source: Platonus, working curriculum for the 2026–2027 academic year.
← Programme curriculum